1. Field of the Invention
The present invention relates to fall-through memory arrays in general and, in particular, to a novel first-in, first-out type buffer memory array.
2. Description of the Prior Art
Memory arrays are formed by a plurality of memory cells which are typically arranged in a plurality of rows and columns. The cells in a particular row store a plurality of bits which form a single word. Among the various types of memory arrays employed in digital equipment, e.g. computers, communications networks, and the like, there is often found a type of memory array called a fall-through memory stack, or simply a stack. For obvious reasons, such arrays are called stacks because, in operation, a plurality of words, either data words or addresses, are sequentially stored in a first word location in the array and then propagated toward the opposite end of the array until the array is filled.
In general, there are two types of such arrays; a first-in, last-out array and a first-in, first-out array.
As its name implies, a first-in, last-out array is so called because out of a series or succession of words transferred to and stored in the array, the first word stored therein is the last word to be retrieved therefrom. In contrast, a first-in, first-out array (FIFO) is so called because out of a series or succession of words transferred to and stored in the array, the first-word stored therein is the first word retrieved therefrom.
The latter type of array, namely the first-in, first-out type of array, to which the present invention is directed in particular, has, heretofore, been implemented in a number of ways.
In describing the operation of such arrays it is convenient to characterize the operation of each cell in the array by defining its operation in terms of a holding mode and a transferring mode. The holding mode is defined as that mode of operation of a particular memory cell during which time it is holding data in a more or less static sense. On the other hand, the transferring mode is defined as that mode of operation during which the contents, i.e., a logical 1 or a logical 0, of a particular memory cell is being transferred to an adjacent memory cell in the same column of memory cells in the memory array. Typically, the contents of all memory cells in a row in a memory array are transferred concurrently to an adjacent row in the array during the transferring mode, thereby transferring an entire word from one row to an adjacent row.
In typical prior art first-in, first-out type memory arrays, each memory cell in a row of memory cells was coupled to a single word line. Control potentials on the word line determined whether the memory cell was operating in a holding mode or in a transferring mode.
In operation, in the transferring mode of prior art arrays, a low going pulse was used to transfer the contents of one memory cell to another in the same column of the array; however, in practice, it was difficult to insure reliable operation over a wide range of temperature and power supply voltages. If, for example, due to temperature and power supply fluctuations, the pulse did not go low enough, no transfer would occur. If the pulse went too low, the contents of adjacent memory cells would uncontrollably transfer beyond the row in which it is desired to receive data. A transistor circuit of the type referred to which uses low going pulses to effect a word transfer in a first-in, first-out type memory array is shown at node 90 in FIG. 2D and described in column 3, line 30, et seq. of U.S. Pat. No. 4,151,609, issued on Apr. 24, 1979 to William E. Moss and assigned to the assignee of the present application, and which is hereby incorporated by reference.